? semiconductor components industries, llc, 2010 december, 2010 ? rev. 0 1 publication order number: nb7vq14m/d nb7vq14m 1.8v/2.5v/3.3v 8ghz / 14gbps differential 1:4 clock / data cml fanout buffer w/ selectable input equalizer multi ? level inputs w/ internal termination description the nb7vq14m is a high performance differential 1:4 cml fanout buffer with a selectable equalizer receiver. when placed in series with a clock /data path operating up to 8 ghz or 14 gb/s, respectively, the nb7vq14m inputs will compensate the degraded signal transmitted across a fr4 pcb backplane or cable interconnect and output four identical cml copies of the input signal with a 1.8 v, 2.5 v or 3.3 v power supply. therefore, the serial data rate is increased by reducing inter ? symbol interference (isi) caused by losses in copper interconnect or long cables. the equalizer enable pin (eqen) allows the in/in inputs to either flow through or bypass the equalizer section. control of the equalizer function is realized by setting eqen; when eqen is set low, the in/in inputs bypass the equalizer. when eqen is set high, the in/in inputs flow through the equalizer. the default state at start ? up is low. as such, nb7vq14m is ideal for sonet, gige, fiber channel, backplane and other clock/data distribution applications. the differential inputs in corporate internal 50 termination resistors that are accessed through the vt pin. this feature allows the nb7vq14m to accept various logic level standards, such as l vpecl, cml or lvds. the 1:4 fanout design was optimized for low output skew applications. the nb7vq14m is a member of the gigacomm ? family of high performance clock products. features ? input data rate > 14 gb/s, typical ? input clock frequency > 8 ghz, typical ? 165 ps typical propagation delay ? 30 ps typical rise and fall times ? < 15 ps maximum output skew ? < 0.8 ps maximum rms clock jitter ? < 10 ps pp of data dependent jitter ? differential cml outputs, 400 mv peak ? to ? peak, typical ? selectable input equalization ? operating range: v cc = 1.71 v to 3.6 v with gnd = 0 v ? internal input termination resistors, 50 ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices http://onsemi.com *for additional marking information, refer to application note and8002/d. marking diagram* a = assembly location l = wafer lot y = year w = work week = pb ? free package qfn ? 16 mn suffix case 485g 16 nb7v q14m alyw 1 see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information (note: microdot may be in either location) 1 eq simplified block diagram
nb7vq14m http://onsemi.com 2 figure 1. detailed block diagram of nb7vq14m q2 q2 q1 q1 q0 q0 q3 q3 0 1 in vt in eq eqen (equalizer enable) multi ? level inputs lvpecl, lvds, cml cml outputs 50 50 75 k 2:1 mux vrefac v cc gnd
nb7vq14m http://onsemi.com 3 eqen q3 q3 v cc gnd q0 q0 v cc q1 q1 q2 q2 in vt vrefac in 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb7vq14m exposed pad (ep) figure 2. qfn ? 16 pinout (top view) table 1. equalizer enable function eqen function 0 in / in inputs by ? pass the equalizer section 1 inputs flow through the equalizer table 2. pin description pin name i/o description 1 in lvpecl, cml, lvds input non ? inverted differential input. note 1. 2 vt internal 100 center ? tapped termination pin for in / in 3 vrefac output voltage reference for capacitor ? coupled inputs, only 4 in lvpecl, cml, lvds input inverted differential input. note 1. 5 eqen lvcmos input equalizer enable input; pin will default low when left open (has internal pull ? down resistor) 6 q3 cml output inverted differential output. typically terminated with 50 resistor to v cc . 7 q3 cml output non ? inverted differential output. typically terminated with 50 resistor to v cc . 8 vcc ? positive supply voltage 9 q2 cml output inverted differential output. typically terminated with 50 resistor to v cc . 10 q2 cml output non ? inverted differential output. typically terminated with 50 resistor to v cc . 11 q1 cml output inverted differential output. typically terminated with 50 resistor to v cc . 12 q1 cml output non ? inverted differential output. typically terminated with 50 resistor to v cc . 13 vcc ? positive supply voltage 14 q0 cml output inverted differential output. typically terminated with 50 resistor to v cc . 15 q0 cml output non ? inverted differential output. typically terminated with 50 resistor to v cc . 16 gnd ? negative supply voltage ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be electrically and thermally con- nected to gnd on the pc board. 1. in the dif ferential configuration when the input termination pin (vt) is connected to a common termination voltage or left open, and if n o signal is applied on in / in input, then, the device will be susceptible to self ? oscillation. 2. all vcc and gnd pins must be externally connected to a power supply for proper operation.
nb7vq14m http://onsemi.com 4 table 3. attributes characteristics value esd protection human body model machine model > 2 kv > 200v r pd ? eqen input pulldown resistor 75 k moisture sensitivity (note 3) 16 ? qfn level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 210 meets or exceeds jedec spec eia/jesd78 ic latchup test 3. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply ? core gnd = 0 v 4.0 v v io positive input/output voltage gnd = 0 v ? 0.5 to v cc + 0.5 v v inpp differential input voltage |in ? in | 1.89 v i in input current through r t (50 resistor) 40 ma i out output current through r t (50 resistor) 40 ma i vfrefac vrefac sink/source current 1.5 ma t a operating temperature range 16 qfn ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm 16 qfn 16 qfn 42 35 c/w c/w jc thermal resistance (junction ? to ? case) (note 4) 16 qfn 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 4. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb7vq14m http://onsemi.com 5 table 5. dc characteristics, multi ? level inputs v cc = 1.71 v to 3.6 v; gnd = 0 v; t a = ? 40 c to 85 c (note 5) symbol characteristic min typ max unit power supply current v cc power supply voltage v cc = 3.3 v v cc = 2.5 v v cc = 1.8 v 3.135 2.375 1.71 3.3 2.5 1.8 3.6 2.625 1.89 v i cc power supply current (inputs and outputs open) 170 210 ma cml outputs (note 6) v oh output high voltage v cc = 3.3 v v cc = 2.5 v v cc = 1.8 v v cc ? 30 3270 2470 1770 v cc ? 5 3295 2495 1795 v cc 3300 2500 1800 mv v ol output low voltage v cc = 3.3 v v cc = 2.5 v v cc = 1.8 v v cc ? 525 2775 1975 1275 v cc ? 425 2875 2075 1375 v cc ? 325 2975 2175 1475 mv differential input driven single ? ended (see figures 5 and 7) (note 7) v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v th input threshold reference voltage range (note 8) 1050 v cc ? 100 mv v ise single ? ended input voltage amplitude (v ih ? v il ) 200 2800 mv vrefac v refac output reference voltage @ 100 a for capacitor coupled inputs, only (note 9) v cc = 3.3 v v cc = 2.5 v v cc = 1.8 v v cc ? 650 2650 1850 1150 v cc ? 500 2800 2000 1300 v cc ? 350 2950 2150 1450 mv differential inputs driven differentially (see figures 6 and 8) (note 9) v ihd differential input high voltage 1200 v cc mv v ild differential input low voltage 0 v ihd ? 100 mv v id differential input voltage (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration) (note 10) (figure 9) 1050 v cc ? 50 mv i ih input high current in / in , (vt open) ? 150 150 a i il input low current in / in , (vt open) ? 150 150 a control inputs (eqen) v ih input high voltage for control pins v cc x 0.65 v cc v v il input low voltage for control pins gnd v cc x 0.35 v i ih input high current ? 150 150 a i il input low current ? 150 150 a termination resistors r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . 6. cml outputs loaded with 50 to v cc for proper operation. 7. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 8. v th is applied to the complementary input when operating in single ? ended mode. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the crosspoint side of the dif ferential input signal.
nb7vq14m http://onsemi.com 6 table 6. ac characteristics v cc = 1.71 v to 3.6 v; gnd = 0 v; t a = ? 40 c to 85 c (note 11) symbol characteristic min typ max unit f max maximum input clock frequency; v out 200 mv 7 8.5 ghz f datamax maximum operating data rate nrz, (prbs23) 10 14 gbps v outpp output voltage amplitude, eqen = 0 or 1 (note 15) f in 7ghz (see figure 10) 200 400 mv t plh , t phl propagation delay in to q x 125 175 225 ps t skew duty cycle skew (note 12) output ? output within device skew device to device skew 3 15 15 50 ps t dc output clock duty cycle (reference duty cycle = 50%) f in 7ghz 40 50 60 % n phase noise, fin = 1 ghz 10 khz 100 khz 1 mhz 10 mhz 20 mhz 40 mhz ? 134 ? 136 ? 150 ? 151 ? 151 ? 151 dbc t n integrated phase jitter f in = 1 ghz, 12 khz ? 20 mhz offset (rms) 35 fs t jitter rms random clock jitter (note 13) f in 7 ghz peak ? to ? peak data dependent jitter (note 14) f in 14 gbps eqen = 0 ( 3? fr4) f in 10 gbps eqen = 1 (12? fr4) 0.2 0.8 10 10 ps rms ps pk ? pk ps pk ? pk v inpp input voltage swing/sensitivity (differential configuration) (note 15) 100 1200 mv t r t f output rise/fall times @ 1.0 ghz qx, qx (20% ? 80%) 15 30 45 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured by forcing v inpp 400mv from a 50% duty cycle clock source. all loading with an external r l = 50 to v cc . input edge rates 40 ps (20% ? 80%). 12. skew is measured between outputs under identical transitions and conditions @ 0.5 ghz. duty cycle skew is measured between dif ferential outputs using the deviations of the sum of tpw ? and tpw+ @ 0.5 ghz. 13. additive rms jitter with 50% duty cycle clock signal. 14. additive peak ? to ? peak data dependent jitter with input nrz data at prbs23. 15. input and output voltage swings are single ? ended measurements operating in a differential mode. 600 500 400 300 200 100 0 08 12 7 6 5 34 figure 3. clock output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typical) f in , clock input frequency (ghz) output voltage amplitude (mv) q amp (mv) 910
nb7vq14m http://onsemi.com 7 figure 4. input structure 50 50 v t v cc in in in v th in v th figure 5. differential input driven single ? ended v ih v il in in figure 6. differential inputs driven differentially v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th figure 7. v th diagram in figure 8. differential inputs driven differentially v ihd v ild v id = |v ihd(in) ? v ild(in)| in in v ild(max) v ihd(max) v ihd v ild v ihd(min) v ild(min) v cmr gnd v id = v ihd ? v ild v cc inx inx q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (in) ? v il (in) figure 9. v cmr diagram figure 10. ac reference measurement v cmrmax v cmrmin
nb7vq14m http://onsemi.com 8 lvpecl driver v cc gnd/v ee z o = 50 v t = v cc ? 2 v z o = 50 nb7vq14m in 50 50 in gnd figure 11. lvpecl interface lvds driver v cc gnd z o = 50 v t = open z o = 50 nb7vq14m in 50 50 in gnd figure 12. lvds interface v cc v cc cml driver v cc gnd z o = 50 v t = v cc z o = 50 nb7vq14m in 50 50 in gnd v cc figure 13. standard 50 load cml interface differential driver v cc gnd z o = 50 vt = v refac * z o = 50 nb7vq14m in 50 50 in gnd v cc figure 14. capacitor ? coupled differential interface (v t connected to v refac ) *v refac bypassed to ground with a 0.01 f capacitor differential driver v cc gnd z o = 50 vt = v refac * nb7vq14m in 50 50 in gnd v cc figure 15. capacitor ? coupled single ? ended interface (v t connected to v refac )
nb7vq14m http://onsemi.com 9 figure 16. typical cml output structure and termination v cc 50 50 16 ma 50 50 v cc (receiver) gnd receiver nb7vq14m v cc = v cc (receiver) figure 17. typical nb7vq14m equalizer application and interconnect with prbs23 pattern at 6.5 gbps, eqen = 1 q q vt in v cc in driver dj1 dj2 dj3 fr4 ? 12 inch backplane nb7vq14m equalizer eqen = 1 ordering information device package shipping ? nb7vq14mmng qfn ? 16 (pb ? free) 123 units / rail nb7vq14mmnhtbg qfn ? 16 (pb ? free) 100 / tape & reel NB7VQ14MMNTXG qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb7vq14m http://onsemi.com 10 package dimensions ??? ??? ??? case 485g ? 01 issue e 16x seating plane l d e 0.10 c a a1 e d2 e2 b 1 4 8 9 16 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. b a 0.10 c top view side view bottom view pin 1 location 0.05 c 0.05 c (a3) c note 4 16x 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 0.18 typ l1 detail a l alternate terminal constructions ?? 0.00 0.15 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. recommended 2x 0.50 pitch 1.84 3.30 1 dimensions: millimeters 0.58 16x 2x 0.30 16x outline package 2x 2x 0.10 c a b e/2 soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nb7vq14m/d gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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